SH7764 Datasheet, PDF (69/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
SH-4A (324 MHz max.)
CPU
Cache
FPU
MMU
ILRAM
DMAC (6 channels)
DMAC
(6 channels)
SuperHyway bridge
Debugging
H-UDI
UBC
SHwyPR
Ether
EtherC
E-DMAC
ini
Super- ⁶⁴
Hyway
bridge tgt
64
USB
USB Super-
controller Hyway
PHY
bridge ^tgt
64
ini
SSI (6 channels)
64
SSI
Super-
Hyway
SSI-DMAC bridge
tgt
64
ini
tgt
64
64
ini
tgt
64
64
ini tgt
64 64
SuperHyway bus (108 MHz max., 64 bits)
tgt
64
HPB bridge
INTC
FLCTL
32 16
32
16
32 ¹⁶
32
16
16
32
32
1616
SRC
SCIF0
SCIF1
WDT
16
SCIF2
32
8
WDT
IIC
32
Reset
8
32
32
GPIO
CPG
16
32
16
32 32
32
32
ATAPI
32
64
G2D
64
64
TMU (6 channels)
32
32
TMU (3 channels)
32
32 ₃₂
TMU (3 channels)
32
32
LCDC
32
32
128
128
VDC2
128
128
256
SuperHyway I/F
LCDC I/F
MCU
Pixel bus I/F
Request arbiter
SDRAM controller
Local bus controller
[Legend]
ATAPI: ATAPI controller
CPG: Clock pulse generator
CPU: Central processing unit
DMAC: Direct memory access controller
E-DMAC: Direct memory access controller
for Ethernet controller
EtherC: Ethernet controller
FLCTL: NAND flash memory controller
FPU: Floating-point unit
GPIO: General I/O
G2D: 2D graphics engine
HPB: Peripheral bus bridge
H-UDI: User debugging interface
IIC:
I²C bus interface
INTC: Interrupt controller
LCDC: LCD controller
ILRAM: IL memory
MCU:
Memory controller unit
MMU:
Memory management unit
SCIF:
Serial communication interface with FIFO
SHwpPR: SuperHyway bus packet router
SRC:
Sampling rate converter
SSI:
Serial sound interface
SSI-DMAC: DMAC for serial sound interface
TMU:
Timer unit
UBC:
User break controller
USB:
USB host/function interface
VDC2:
Video display controller 2
WDT:
Watchdog timer
ini:
Port for outputting requests to the bus
tgt:
Port for receiving requests from the bus
Figure 1.1 Block Diagram
Rev. 1.00 Nov. 22, 2007 Page 13 of 1692
REJ09B0360-0100