SH7764 Datasheet, PDF (661/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.11 DMA Start Address Register (ATAPI_DMA_START_ADR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
DSTAA[2:0]
DSTA[25:16]
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DSTA[15:2]
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Initial
Bit
Bit Name Value R/W Description
31 to 29 —
All 0
R
Reserved
28 to 26 DSTAA[2:0] 0
R/W DSTAA sets DMA start SDRAM area in descriptor
operation mode.
001: SDRAM area 1
010: SDRAM area 2
Other than above: Setting prohibited.
25 to 2 DSTA[25:2] 0
R/W DSTA sets a DMA start address that indicates the data
transfer start address in the memory. Bits 25 to 0 are
used to specify the DMA start address in byte.
Since 256-bit address boundary must be kept for DMA
start address, bits 4 to 2 must be set 0, and bits 1 and 0
are ignored.
1, 0
—
All 0
R
Reserved
Notes: 1. This register is valid only when bit 5 (BUSSEL) in the ATAPI Control Register is 1.
2. This address does not change and the set value is retained even after DMA activation.
3. In the 32-bit address mode, bits 28 to 0 should contain the lower 29 bits of the specified
32-bit address.
Rev. 1.00 Nov. 22, 2007 Page 605 of 1692
REJ09B0360-0100