SH7764 Datasheet, PDF (496/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.14 Interrupt Mask Register (INT2MSKR)
INT2MSKR is a 32-bit readable/writable register that sets masking for each source indicated in
the interrupt source register. Interrupts whose corresponding bits in INT2MSKRG are set to 1 are
not notified to the CPU.
INT2MSKR is initialized to H'FFFF FFFF (mask state) by a reset.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
— GPIO
—
SRC FLCTL — ATAPI SSI_B —
SSI_A SSI_A
CH2 CH1
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R R/W R R/W R/W R R/W R/W R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSI_A SSI_A
CH0 DMA0
G2D
—
—
—
— DMAC H-UDI — WDT SCIF1 SCIF0 — TMU1 TMU0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R
R
R
R R/W R/W R R/W R/W R/W R R/W R/W
Bit
Bit Name
31 to 26 —
Initial
Value
All 1
25
GPIO
1
24
—
1
23
SRC
1
22
FLCTL
1
21
—
1
20
ATAPI
1
19
SSI_B
1
18
—
1
17
SSI_ACH2 1
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
Function
Description
Reserved
Masks interrupts for
These bits are always read as 1. The ^{each peripheral}
write value should always be 1.
module.
Masks GPIO interrupts
[When writing]
Reserved
0: Invalid
This bit is always read as 1. The write
value should always be 1.
1: Interrupts are
masked
Masks SRCOVF interrupts
[When reading]
Masks FLCTL interrupts
Reserved
0: No mask setting
1: Mask setting
This bit is always read as 1. The write
value should always be 1.
Masks ATAPI interrupts
Masks SSI_B interrupts
Reserved
This bit is always read as 1. The write
value should always be 1.
Masks SSI_A (SSICH2) interrupts
Rev. 1.00 Nov. 22, 2007 Page 440 of 1692
REJ09B0360-0100