SH7764 Datasheet, PDF (492/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.12 Interrupt Source Register (Mask State is affected) (INT2A1)
INT2A1 (mask state is affected) is a 32-bit read-only register that indicates interrupt source
modules. Note that if interrupt masking is set in the interrupt mask register, INT2A1 does not
indicate a source module in a corresponding bit. To check whether interrupts are generated,
regardless of the state of the interrupt mask register, use INT2A0
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
— GPIO —
SRC FLCTL — ATAPI SSI_B —
SSI_A SSI_A
CH2 CH1
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SSI_A SSI_A
CH0 DMA0
G2D
—
—
—
— DMAC H-UDI — WDT SCIF1 SCIF0 — TMU1 TMU0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
31 to 26 —
All 0
25
GPIO
0
24
—
0
23
SRC
0
22
FLCTL 0
21
—
0
20
ATAPI 0
19
SSI_B 0
18
—
0
17
SSI_ACH 0
2
16
SSI_ACH 0
1
R/W Function
Description
R
Reserved
Indicates interrupt
These bits are always read as 0. ^{sources for each}
peripheral module
R
Indicates GPIO interrupt source _{(INT2A1 is affected by}
R
Reserved
This bit is always read as 0.
the state of the
interrupt mask
register).
R
Indicates SRCOVF interrupt
source
0: No interrupts
1: Interrupts are
R
Indicates FLCTL interrupt source
generated
R
Reserved
Note: Reading the
This bit is always read as 0.
INTEVT code
R
Indicates ATAPI interrupt source
R
Indicates SSI_B interrupt source
notified to the
CPU directly
can identify
R
Reserved
This bit is always read as 0.
interrupt
sources. In this
case, reading
R
Indicates SSI_A (SSICH2)
INT2A1 is not
interrupt source
necessary.
R
Indicates SSI_A (SSICH1)
interrupt source
Rev. 1.00 Nov. 22, 2007 Page 436 of 1692
REJ09B0360-0100