SH7764 Datasheet, PDF (1496/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Watchdog Timer and Reset
EXTAL
input
CLKOUT
output
WDT overflow
signal
STATUS[1:0]
output
HL (sleep)
HH (reset)
LL (normal)
WDT reset
setup time
WDT reset
holding time
Figure 29.7 STATUS Output by Watchdog timer overflow Power-On Reset
during Sleep Mode
Rev. 1.00 Nov. 22, 2007 Page 1440 of 1692
REJ09B0360-0100