SH7764 Datasheet, PDF (616/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
Bit
Bit Name Initial Value R/W Description
5
STM
0
R
Slave Transmit Mode
Indicates whether the current slave transmit
mode is read or write. When this bit is set to 1,
the mode is write. When this bit is set to 0, the
mode is read. This status bit does not cause
an interrupt.
This bit is automatically cleared by hardware
when the SIE bit (bit 2 in the slave control
register) is set to 0 or when the SSR bit (bit 4
in the slave status register) is set to 1.
4
SSR
0
R/W* Slave Stop Received
A stop condition has been output on the bus.
This status bit becomes active after the rising
edge of SDA during the stop bit.
3
SDE
0
R/W* Slave Data Empty
Indicates that data to be transmitted has been
loaded into the shift register. At the start of
byte data transmission, the contents of the
ICTXD register are loaded into a shift register
ready for outputting data on the bus. This
status bit indicates that data has been loaded
and the ICTXD register is again ready for
further data. This status bit becomes active on
the falling edge of SCL before the first data bit.
During the single-buffer mode, this bit must be
reset every time new data has been written to
the ICTXD register. This is because the slave
holds SCL low to stop the bus while this bit is
set to 1 even if a slave transmission cycle is
started.
2
SDT
0
R/W* Slave Data Transmitted
A byte of data has been transmitted to the bus.
This bit becomes active after the falling edge
of SCL during the last data bit.
Rev. 1.00 Nov. 22, 2007 Page 560 of 1692
REJ09B0360-0100