SH7764 Datasheet, PDF (122/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Instruction
Operation
Instruction Code
Privileged T Bit New
LDC
Rm,SSR
Rm → SSR
0100mmmm00111110 Privileged — —
LDC
Rm,SPC
Rm → SPC
0100mmmm01001110 Privileged — —
LDC
Rm,DBR
Rm → DBR
0100mmmm11111010 Privileged — —
LDC
Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged — —
LDC.L
@Rm+,SR
(Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 Privileged LSB —
LDC.L
@Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 —
——
LDC.L
@Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Privileged — —
LDC.L
@Rm+,SGR (Rm) → SGR, Rm + 4 → Rm 0100mmmm00110110 Privileged — —
LDC.L
@Rm+,SSR (Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 Privileged — —
LDC.L
@Rm+,SPC (Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 Privileged — —
LDC.L
@Rm+,DBR (Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110 Privileged — —
LDC.L
@Rm+,Rn_
BANK
(Rm) → Rn_BANK,
Rm + 4 → Rm
0100mmmm1nnn0111 Privileged — —
LDS
Rm,MACH
Rm → MACH
0100mmmm00001010 —
——
LDS
Rm,MACL
Rm → MACL
0100mmmm00011010 —
——
LDS
Rm,PR
Rm → PR
0100mmmm00101010 —
——
LDS.L
@Rm+,MACH (Rm) → MACH, Rm + 4 → 0100mmmm00000110 —
Rm
——
LDS.L
@Rm+,MACL (Rm) → MACL, Rm + 4 → 0100mmmm00010110 —
Rm
——
LDS.L
@Rm+,PR
(Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 —
——
LDTLB
PTEH/PTEL (/PTEA) → TLB 0000000000111000 Privileged — —
MOVCA.L R0,@Rn
R0 → (Rn) (without fetching 0000nnnn11000011 —
cache block)
——
NOP
No operation
0000000000001001 —
——
OCBI
@Rn
Invalidates operand cache 0000nnnn10010011 —
block
——
OCBP
@Rn
Writes back and invalidates 0000nnnn10100011 —
operand cache block
——
OCBWB @Rn
Writes back operand cache 0000nnnn10110011 —
block
——
PREF
@Rn
(Rn) → operand cache
0000nnnn10000011 —
——
PREFI
@Rn
Reads 32-byte instruction 0000nnnn11010011 
block into instruction cache
 New
RTE
Delayed branch, SSR/SPC 0000000000101011 Privileged — —
→ SR/PC
Rev. 1.00 Nov. 22, 2007 Page 66 of 1692
REJ09B0360-0100