SH7764 Datasheet, PDF (638/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
16.5 Programming Examples
16.5.1 Master Transmitter
In order to set up the master interface to transmit a data packet on the I²C bus, follow the following
procedure:
(1) Load Clock Control Register
1. SCL clock generation divider (SCGD) = H'03
(SCL frequency of 400 kHz)
2. Clock division ratio (CDF) = H'2
(The peripheral clock is 50 MHz and the IIC's internal clock IICck is 16.7 MHz.)
(2) Load Master Control Register (First Data Byte and Address)
1. Master address register = address of slave being accessed and STM1 bit (write mode: 0)
2. Transmit data register = first data byte to be transmitted
3. Master control register = H'89
(MDBS = 1, MIE = 1, ESG = 1)
(3) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDE bits in the master status register).
2. Set the master control register to H'88 (To suspend the data transmission, the master device
will hold the SCL low until the MDE bit is cleared.)
If only one byte of data is transmitted, set the master control register to H'8A, meaning that the
stop generation is enabled. This generates a stop on the bus as soon as one byte has been
transmitted.
3. Reset the MAT bit.
(4) Monitor Transmission of Data
1. Wait for master event, MDE in the master status register.
2. Transmit data register = subsequent data.
3. Reset the MDE bit.
Clear MDE after setting the last byte to be transmitted. After the last byte data is transmitted,
MDE is generated. To clear the MDE, you must set the master control register to H'8A.
(Set the force stop control bit).
Rev. 1.00 Nov. 22, 2007 Page 582 of 1692
REJ09B0360-0100