SH7764 Datasheet, PDF (107/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Section 3 Instruction Set
The SH-4A's instruction set is implemented with 16-bit fixed-length instructions. The SH-4A can
use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory
access. Single-precision floating-point data (32 bits) can be moved to and from memory using
longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and
from memory using longword size. When the SH-4A moves byte-size or word-size data from
memory to a register, the data is sign-extended.
3.1 Execution Environment
(1) PC
At the start of instruction execution, the PC indicates the address of the instruction itself.
(2) Load-Store Architecture
The SH-4A has a load-store architecture in which operations are basically executed using
registers. Except for bit-manipulation operations such as logical AND that are executed directly in
memory, operands in an operation that requires memory access are loaded into registers and the
operation is executed between the registers.
(3) Delayed Branches
Except for the two branch instructions BF and BT, the SH-4A's branch instructions and RTE are
delayed branches. In a delayed branch, the instruction following the branch is executed before the
branch destination instruction.
(4) Delay Slot
This execution slot following a delayed branch is called a delay slot. For example, the BRA
execution sequence is as follows:
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