SH7764 Datasheet, PDF (457/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
As explained above, a repeat mode transfer enables sequential voice compression by changing
buffer for storing data received consequentially and a data buffer for processing signals
alternately.
12.4.6 Reload Mode Transfer
In a reload mode transfer, according to the settings of bits RPT[2:0] in CHCR, the value set in
SARB/DARB is set to SAR/DAR and the value of bits TCRB[23:16] is set in bits TCRB[7:0] at
each transfer set in the bits TCRB[7:0], and the transfer is repeated until TCR becomes 0 without
specifying the transfer settings again. A reload mode transfer is effective when repeating data
transfer with specific area. Figure 12.12 shows the operation of reload mode transfer.
DMAC
Transfer request
Reload controller
Bits RPT[2:0]
CHCR
TCR
Transfer counter
TCRB
Reload signal
Reload counter
SAR/DAR
SARB/DARB
Figure 12.12 Reload Mode Transfer
When a reload mode transfer is executed, TCRB is used as a reload counter. Set TCRB according
to section 12.3.6, DMA Transfer Count Registers (TCRB0 to TCRB3).
Rev. 1.00 Nov. 22, 2007 Page 401 of 1692
REJ09B0360-0100