SH7764 Datasheet, PDF (1386/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
Initial
Bit
Bit Name Value R/W Description
1
IINT
1
R/(W)* Input Data FIFO Empty Interrupt Request Flag
Indicates that the number of data units in the input
FIFO has become equal to or smaller than the
triggering number specified by the IFTRG1 and
IFTRG0 bits in the SRC input data control register
(SRCIDCTRL).
[Clearing conditions]
• When 0 has been written to the IINT bit after
reading IINT = 1.
• When the DMAC has transferred data to the input
FIFO resulting in the number of data units in the
FIFO exceeding that of the specified triggering
number.
[Setting condition]
• When the number of data units in the input FIFO
has become equal to or smaller than the specified
triggering number.
• When 1 has been written to the CL bit in
SRCCTRL.
0
OINT
0
R/(W)* Output Data FIFO Full Interrupt Request Flag
Indicates that the number of data units in the output
FIFO has become equal to or greater than the
triggering number specified by the OFTRG[1:0] bits in
the SRC output data control register (SRCODCTRL).
[Clearing conditions]
• When 0 has been written to the OINT bit after
reading OINT = 1.
• When the DMAC has transferred data from the
output FIFO resulting in the number of data units
in the FIFO being less than the specified triggering
number.
[Setting condition]
• When the number of data units in the output FIFO
has become equal to or greater than the specified
triggering number.
Note: * Only 0 can be written after having read as 1.
Rev. 1.00 Nov. 22, 2007 Page 1330 of 1692
REJ09B0360-0100