SH7764 Datasheet, PDF (1338/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
25.3 Register Descriptions
Table 25.2 shows the FLCTL register configuration. Table 25.3 shows the register state in each
processing mode.
Table 25.2 Register Configuration of FLCTL
Name
Abbreviation R/W
Common control register
FLCMNCR R/W
Command control register
FLCMDCR R/W
Command code register
FLCMCDR R/W
Address register
FLADR
R/W
Address register 2
FLADR2
R/W
Data register
FLDATAR
R/W
Data counter register
FLDTCNTR R/W
Interrupt DMA control register FLINTDMACR R/W
Ready busy timeout setting
register
FLBSYTMR R/W
Ready busy timeout counter FLBSYCNT R
Data FIFO register
FLDTFIFO
R/W
Control code FIFO register FLECFIFO R/W
Transfer control register
FLTRCR
R/W
Area P4
Address
H'FFE9 0000
H'FFE9 0004
H'FFE9 0008
H'FFE9 000C
H'FFE9 003C
H'FFE9 0010
H'FFE9 0014
H'FFE9 0018
H'FFE9 001C
H'FFE9 0020
H'FFE9 0024/
H'FFE9 0050
H'FFE9 0028/
H'FFE9 0060
H'FFE9 002C
Area 7
Address
H'1FE9 0000
H'1FE9 0004
H'1FE9 0008
H'1FE9 000C
H'1FE9 003C
H'1FE9 0010
H'1FE9 0014
H'1FE9 0018
H'1FE9 001C
H'1FE9 0020
H'1FE9 0024/
H'1FE9 0050
H'1FE9 0028/
H'1FE9 0060
H'1FE9 002C
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
8
Rev. 1.00 Nov. 22, 2007 Page 1282 of 1692
REJ09B0360-0100