SH7764 Datasheet, PDF (265/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Virtual address
31
Section 8 Caches
13 12 10
54 2 0
22
MMU
19
Entry selection
Address array
8
(way 0 to way 3)
0
Tag
V
[12:5]
Longword (LW) selection
Data array
3
(way 0 to way3)
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
LRU
255 _{19 bits 1 bit}
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 6 bits
Comparison
(Way 0 to way 3)
Read data
Hit signal
Figure 8.2 Configuration of Instruction Cache (Cache size = 32 Kbytes)
• Tag
Stores the upper 19 bits of the 29-bit physical address of the data line to be cached. The tag is
not initialized by a power-on.
• V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset.
• U bit (dirty bit)
• The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 8.6,
Memory-Mapped Cache Configuration). The U bit is initialized to 0 by a power-on reset.
Rev. 1.00 Nov. 22, 2007 Page 209 of 1692
REJ09B0360-0100