SH7764 Datasheet, PDF (615/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
Bit
Bit Name Initial Value R/W Description
0
FNA
0
R/W Forced Non Acknowledgement
In the slave receive mode, the level of this bit is
sent to the transmitting device as the
acknowledge signal. This bit is set to 0 during the
period that the data packet is being received, and
set to 1 on completion of data reception.
Forced non acknowledgement is returned to the
master during slave reception.
When the slave has received the last byte of data
in a data packet, the slave communicates with
the master by sending a nack, meaning that the
acknowledgement is not driven. The master
issues a stop on the bus after receiving a nack.
The setting of this bit does not affect the
acknowledgement of the slave address.
16.3.2 Slave Status Register (ICSSR)
The status bits (bits 0 to 4) in the slave status register are cleared by writing 0 to the respective
status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and
STM bits).
Bit: 7

Initial value: 0
R/W: R
6
5
4
3
2
1
0
GCAR STM SSR SDE SDT SDR SAR
0
0
0
0
0
0
0
R R R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name Initial Value R/W Description
7
—
0
R
Reserved
The write value should always be 0.
6
GCAR
0
R
General Call Address Received
Indicates that the address received from the
bus is a general call address (00H). This status
bit does not cause an interrupt.
This bit is automatically cleared by hardware
when the SIE bit (bit 2 in the slave control
register) is set to 0 or when the SSR bit (bit 4
in this register) is set to 1.
Rev. 1.00 Nov. 22, 2007 Page 559 of 1692
REJ09B0360-0100