SH7764 Datasheet, PDF (1313/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.14 Interrupt Output Control Register (SGINTCNT)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0










VSYNC
 _{_MASK} 


VSYNC_
STATUS
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R R R R/WC0
Initial
Bit
Bit Name Value
R/W Description
31 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
4
VSYNC_ 0
MASK
R/W
Masks the VSYNC interrupt*¹.
0: Enables interrupts
1: Masks interrupts
3 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
VSYNC_ 1
STATUS
R/WC0 Indicates the VSYNC interrupt status*².
0: An interrupt has occurred
1: No interrupts have occurred
Notes: 1. Writing 1 to the interrupt mask bit clears the interrupt status.
2. Writing 0 to the interrupt status bit clears the interrupt status.
The VSYNC_STATUS value is output through the db_n_int_n signal terminal (low-active signal)
of the VDC block.
Rev. 1.00 Nov. 22, 2007 Page 1257 of 1692
REJ09B0360-0100