SH7764 Datasheet, PDF (234/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
EPR[1]: Writing in user mode
EPR[0]: Execution in user mode (instruction fetch)
• C: Cacheability bit
Indicates whether a page is cacheable.
0: Not cacheable
1: Cacheable
When the control register area is mapped, this bit must be cleared to 0.
• D: Dirty bit
Indicates whether a write has been performed to a page.
0: Write has not been performed.
1: Write has been performed.
• WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
Rev. 1.00 Nov. 22, 2007 Page 178 of 1692
REJ09B0360-0100