SH7764 Datasheet, PDF (620/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
16.3.5 Master Control Register (ICMCR)
Bit: 7
6
5
4
3
MDBS FSCL FSDA OBPC MIE
Initial value: 0
R/W: R

0
0
R/W R/W R/W R/W
2
TSBE
0
R/W
1
FSB
0
R/W
0
ESG
0
R/W
Bit
Bit Name Initial Value R/W Description
7
MDBS
0
R/W Master Data Buffer Select
This bit is used to select the data buffer. The
double-buffer mode and singe-buffer mode are
available.
When this bit is set to 0, the double-buffer
mode is selected. During a reception, as long
as both buffers are full and the MDR flag has
not been cleared, SCL is held low. When the
MDR flag is cleared, the low level state of SCL
is released.
When this bit is set to 1, the single-buffer mode
is selected. SCL will be held low from the
timing when the receive data register acquires
the data packet until the MDR flag is cleared.
0: Double-buffer mode
1: Single-buffer mode
6
FSCL
Undefined R/W Forced SCL
This bit controls the status of the SCL pin
(reading reflects the current level on the I²C
bus). When the OBPC bit is set, this bit directly
controls the SCL line on the bus.
During a read cycle, the level on this bit (which
includes the reset level) will change depending
on the level on SCL since it reflects the level
on the SCL.
5
FSDA
Undefined R/W Forced SDA
This bit controls the status of the SDA pin
(reading reflects the busy status level on the
SDA). When the OBPC bit is set then this bit
directly controls the SDA line on the bus.
During a read cycle, the level of this bit (which
includes the reset level) will show the busy
status of the I²C bus (1 for busy; 0 for not
busy).
Rev. 1.00 Nov. 22, 2007 Page 564 of 1692
REJ09B0360-0100