SH7764 Datasheet, PDF (831/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.13 Transmit FIFO Underrun Counter (TFUCR)
TFUCR is a register that indicates the count of underruns having occurred in the transmit FIFO.
The count value is cleared to 0 by writing any value to this register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UNDER[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 16 
Initial
Value
All 0
15 to 0 UNDER All 0
[15:0]
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit FIFO Underflow Count
Indicates the count of underflows having occurred in the
transmit FIFO.
The counter stops when the count value reaches
H'FFFF.
Rev. 1.00 Nov. 22, 2007 Page 775 of 1692
REJ09B0360-0100