SH7764 Datasheet, PDF (72/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Classification
Operating mode
control
System control
Symbol
MODE2
MODE1
MODE0
MODE4
MODE3
MODE5
MODE7
MODE8
PRESET
WDTOVF
BREQ
BACK
I/O Name
Function
I
Clock mode set These pins set the clock operating
mode. Do not change the signal
levels on these pins during
operation.
I
Bus mode set These pins set the bus operating
mode. Do not change the signal
levels on these pins during
operation.
I
Endian set
Selects the endian for the CPU. Do
not change the signal level on this
pin during operation.
I
XIN/XOUT pin Enables the external clock or crystal
function set
resonator for the USB.
I
EXTAL/XTAL pin Enables the external clock or crystal
function set
resonator.
I
Power-on reset This LSI enters the power-on reset
state when this signal goes low.
O Watchdog timer Outputs an overflow signal from the
overflow
WDT.
I
Bus-mastership A low level should be input to this pin
request
when an external device requests
the release of the bus mastership.
O Bus-mastership Indicates that the bus mastership
request
acknowledge
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Rev. 1.00 Nov. 22, 2007 Page 16 of 1692
REJ09B0360-0100