SH7764 Datasheet, PDF (888/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
9

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8
BIGEND
0
R/W CFIFO Port Endian Control
Specifies the byte endian for the CFIFO port.
0: Little endian
1: Big endian
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
5
ISEL
0
R/W CFIFO Port Access Direction When DCP is Selected
0: Reading from the buffer memory is selected
1: Writing to the buffer memory is selected
After writing to this bit with the DCP being a selected
pipe, read this bit to check that the written value
agrees with the read value before proceeding to the
next process.
Even if an attempt is made to modify the setting of
this bit during access to the FIFO buffer, the current
access setting is retained until the access is
completed. Then, the modification becomes effective
thus enabling continuous access.
Set this bit and the CURPIPE bits simultaneously.
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 832 of 1692
REJ09B0360-0100