SH7764 Datasheet, PDF (1154/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
• SS = 0 and REL = 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OP CODE = 1000_0010
Reserve (all 0)
Draw Mode
000
Base Address (quad word address)
000
0000
TDX (8 ≤ TDX ≤ 4088)
0 0 0 000 0
TDY (1 ≤ TDY ≤ 4095)
0000
TXOFS (0 ≤ TXOFS ≤ TDX − 1)
000 0
TYOFS (0 ≤ TYOFS ≤ TDY – 1)
Sign
DX1 (-32768 ≤ DX1 ≤ 32767)
Sign
DY1 (-32768 ≤ DY1 ≤ 32767)
Sign
DX2 (-32768 ≤ DX2 ≤ 32767)
Sign
DY2 (-32768 ≤ DY2 ≤ 32767)
Sign
DX3 (-32768 ≤ DX3 ≤ 32767)
Sign
DY3 (-32768 ≤ DY3 ≤ 32767)
Sign
DX4 (-32768 ≤ DX4 ≤ 32767)
Sign
DY4 (-32768 ≤ DY4 ≤ 32767)
• SS = 0 and REL = 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OP CODE = 1000_0010
Reserve (all 0)
Draw Mode
Sign extended Sign
Base Address (longword address)
00
0000
TDX (8 ≤ TDX ≤ 4088)
0 0 0 0 0 00
TDY (1 ≤ TDY ≤ 4095)
0000
TXOFS (0 ≤ TXOFS ≤ TDX − 1)
0 0 00
TYOFS (0 ≤ TYOFS ≤ TDY – 1)
Sign
DX1 (-32768 ≤ DX1 ≤ 32767)
Sign
DY1 (-32768 ≤ DY1 ≤ 32767)
Sign
DX2 (-32768 ≤ DX2 ≤ 32767)
Sign
DY2 (-32768 ≤ DY2 ≤ 32767)
Sign
DX3 (-32768 ≤ DX3 ≤ 32767)
Sign
DY3 (-32768 ≤ DY3 ≤ 32767)
Sign
DX4 (-32768 ≤ DX4 ≤ 32767)
Sign
DY4 (-32768 ≤ DY4 ≤ 32767)
Note: Adding the address (longword: 32-bit units) where the command code is located to the
Base Address (longword: 32-bit units) must result in a quad word address (64-bit units).
Rev. 1.00 Nov. 22, 2007 Page 1098 of 1692
REJ09B0360-0100