SH7764 Datasheet, PDF (890/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
(2) D0FIFOSEL, D1FIFOSEL
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RCNT REW DCLRM DREQE MBW[1:0]
—
BIG
END
—
—
—
—
CURPIPE[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W* R/W R/W R/W R/W R R/W R
R
R
R R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15
RCNT
0
R/W Read Count Mode
Specifies the read mode for the value in the DTLN
bits in DnFIFOCTR.
0: The DTLN bit is cleared when all of the receive
data has been read from the DnFIFO.
(In double buffer mode, the DTLN bit value is
cleared when all the data has been read from a
single plane.)
1: The DTLN bit is decremented when the receive
data is read from the DnFIFO.
When accessing DnFIFO with the BFRE bit set to 1,
set this bit to 0.
14
REW
0
R/W* Buffer Pointer Rewind
Specifies whether or not to rewind the buffer pointer.
0: The buffer pointer is not rewound.
1: The buffer pointer is rewound.
When the selected pipe is in the receiving direction,
setting this bit to 1 while the FIFO buffer is being
read allows re-reading the FIFO buffer from the first
data (in double buffer mode, re-reading the currently-
read FIFO buffer plane from the first data is allowed).
Do not set REW to 1 simultaneously with modifying
the CURPIPE bits. Before setting REW to 1, be sure
to check that FRDY is 1.
When accessing DnFIFO with the BFRE bit set to 1,
do not set this bit to 1 in the state in which the short
packet data has been read out.
To re-write to the FIFO buffer again from the first
data for the pipe in the transmitting direction, use the
BCLR bit.
Rev. 1.00 Nov. 22, 2007 Page 834 of 1692
REJ09B0360-0100