SH7764 Datasheet, PDF (900/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
15

14
BCHGE
13

12
DTCHE
11
ATTCHE
10 to 7 
6
EOFERRE
5
SIGNE
Initial
Value
0
0
0
0
0
All 0
0
0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W USB Bus Change Interrupt Enable
Enables or disables the USB interrupt output when
the BCHG interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Disconnection Detection Interrupt Enable
Enables or disables the USB interrupt output when
the DTCH interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
R/W Connection Detection Interrupt Enable
Enables or disables the USB interrupt output when
the ATTCH interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W EOF Error Detection Interrupt Enable
Enables or disables the USB interrupt output when
the EOFERR interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
R/W Setup Transaction Error Interrupt Enable
Enables or disables the USB interrupt output when
the SIGN interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 1.00 Nov. 22, 2007 Page 844 of 1692
REJ09B0360-0100