SH7764 Datasheet, PDF (658/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.8 Descriptor Table
The descriptor table consists of the termination flag, the descriptor DMA start address (DDSTA),
and the descriptor DMA transfer count (DDTRC).
Descriptor Table Map in Memory
Address
DTBA
DTBA + 4
DTBA + 8
DTBA + 12
Data description
The first termination flag (bit 31=0) and DDSTAA/DDSTA
The first DDTRC
The second termination flag (bit 31=0) and DDSTAA/DDSTA
The second DDTRC
DTBA + 8 × (n − 1)
DTBA + 8 × (n − 1) + 4
The n-th termination flag (bit 31=1) and DDSTAA/DDSTA
The n-th DDTRC
Rev. 1.00 Nov. 22, 2007 Page 602 of 1692
REJ09B0360-0100