SH7764 Datasheet, PDF (1306/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Initial
Bit
Bit Name Value
R/W Description
2, 1
AMOD[1:0] 00
R/W These bits specify the α processing mode.
00: Initial α value (does not change the value)
01: α value addition
10: α value subtraction
11: Setting prohibited
0
AEN
0
R/W Enables or disables α control.
0: Disables α control (same as α value = 1)
1: enables α control
Note: Layer 1 is the bottom image which has no α control target, so the above settings are
prohibited for layer 1.
When AEN = 1 and WE = 1, the α value is loaded in the internal circuits in synchronization with
Vsync.
If AMOD[1:0] = [0 0], the α value specified in DEFA is applied to the video area.
If AMOD[1:0] = [0 1], the ACOEF value is added to the DEFA value according to the field rate
and the result is applied to the video area as the α value. When the α value becomes 255 or larger,
processing stops (fade-out).
If AMOD[1:0] = [1 0], the ACOEF value is subtracted from the DEFA value according to the field
rate and the result is applied to the video area as the α value. When the α value becomes 0 or
smaller, processing stops (fade-in).
Table 24.9 α Value and Blending Ratio
α Value (Decimal)
255
254
253
252
1
0
Graphics
256/256
254/256
253/256
252/256
:
2/256
1/256
0/256
Lower-Layer Graphics
0/256
1/256
2/256
3/256
:
253/256
254/256
256/256
Rev. 1.00 Nov. 22, 2007 Page 1250 of 1692
REJ09B0360-0100