SH7764 Datasheet, PDF (1601/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 32 List of Registers
Module
Register Name
P4 Area
Abbreviation R/W Address*²
Area 7
Address*²
Access Remarks
Size
(WPR)*¹
G2D
Rendering control 2
RCL2R
R/W H'FFEA 00F0 H'1FEA 00F0 32
O
Pattern offset
POFSR
R/W H'FFEA 00F8 H'1FEA 00F8 32
O
Coordinate
transformation control
GTRCR
R/W H'FFEA 0100 H'1FEA 0100 32
O
Matrix parameter A
MTRAR
R/W H'FFEA 0104 H'1FEA 0104 32
O
Matrix parameter B
MTRBR
R/W H'FFEA 0108 H'1FEA 0108 32
O
Matrix parameter C
MTRCR
R/W H'FFEA 010C H'1FEA 010C 32
O
Matrix parameter D
MTRDR
R/W H'FFEA 0110 H'1FEA 0110 32
O
Matrix parameter E
MTRER
R/W H'FFEA 0114 H'1FEA 0114 32
O
Matrix parameter F
MTRFR
R/W H'FFEA 0118 H'1FEA 0118 32
O
Matrix parameter G
MTRGR
R/W H'FFEA 011C H'1FEA 011C 32
O
Matrix parameter H
MTRHR
R/W H'FFEA 0120 H'1FEA 0120 32
O
Matrix parameter I
MTRIR
R/W H'FFEA 0124 H'1FEA 0124 32
O
Coordinate
GTROFSXR R/W H'FFEA 0128 H'1FEA 0128 32
O
transformation offset X
Coordinate
GTROFSYR R/W H'FFEA 012C H'1FEA 012C 32
O
transformation offset Y
Z clipping area MIN
ZCLPMINR
R/W H'FFEA 0130 H'1FEA 0130 32
O
Z clipping area MAX ZCLPMAXR R/W H'FFEA 0134 H'1FEA 0134 32
O
Z saturation value MIN ZSATVMINR R/W H'FFEA 0138 H'1FEA 0138 32
O
Notes: 1. WPR command setting
O: Possible
×: Impossible
2. The P4 area addresses shown here are the P4 area addresses in the virtual address
space. The area 7 addresses should be accessed via the area 7 in the physical address
space using the TLB.
If any address not specified here is written to, operation is not guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1545 of 1692
REJ09B0360-0100