SH7764 Datasheet, PDF (408/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
(3) Confirming Reflection of Software Reset
For a software reset, refer to the relevant sections for each module.
To reflect a software reset of the modules correctly on the SH7764, some measures should be
taken to check if a write access has been reflected, similar to memory access. Therefore, after the
module has entered the software reset state, the following processes should be carried out before it
exits the state.
1. When the priority level of the CPU and that of the module to which a software reset is applied
are the same, perform a dummy read three times to any SDRAM area.
2. When the priority level of the CPU is level 3 and that of the module to which a software reset
is applied is level 2, perform a dummy read once to any SDRAM area.
3. When the priority level of the CPU is level 2 and that of the module to which a software reset
is applied is level 3, terminate all the accesses to SDRAM from the level-2 and level-3
modules other than the software-reset-applied module.
11.11 Linear-to-Tiled Memory Address Translation
(1) Tiled Memory Areas
This LSI can modify addresses in the specified range of the connected SDRAM. (For the accesses
from the LCDC, linear addresses are not translated into tilled memory addresses.)
The areas with the modified addresses are called the tiled memory areas. The tiled memory areas
are useful as graphics areas in which two-dimensional accesses occur frequently. In these areas,
each graphic data area of 32B × 16 lines is called a tile, and a tile unit is assigned the consecutive
512 bytes of memory. This increases the ratio of hitting at an SDRAM page when the locations to
be accessed change frequently in the row direction.
Rev. 1.00 Nov. 22, 2007 Page 352 of 1692
REJ09B0360-0100