SH7764 Datasheet, PDF (773/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.9 Transmit Retry Over Counter Register (TROCR)
TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted
in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed,
this register is incremented by 1. When the value in this register reaches H'FFFFFFFF, count-up is
halted. The counter value is cleared to 0 by a write to this register with any value.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TROC[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TROC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 0 TROC[31:0] All 0 R/W
Description
Transmit Retry Over Count
These bits indicate the number of frames that were
unable to be transmitted in 16 transmission attempts
including the retransfer.
Rev. 1.00 Nov. 22, 2007 Page 717 of 1692
REJ09B0360-0100