SH7764 Datasheet, PDF (82/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Classification
NAND flash
memory controller
(FLCTL)
I/O ports (GPIO)
Symbol
I/O
FCE
O
FD7 to FD0 I/O
FCLE
O
FALE
O
FRE
O
FWE
O
FR/B
I
PA7 to PA0 I/O
PB7 to PB0 I/O
PC7 to PC0 I/O
PD7 to PD0 I/O
PE7 to PE0 I/O
PF7 to PF0 I/O
PG7 to PG0 I/O
PH7 to PH0 I/O
PI4 to PI0 I/O
PJ7 to PJ0 I/O
Name
Chip enable
Data I/O
Command latch
enable
Address latch
enable
Read enable
Write enable
Ready/busy
General port
General port
General port
General port
General port
General port
General port
General port
General port
General port
Function
Chip enable pin.
Command, address, and data I/O.
Command latch enable (CLE).
Asserted when a command is
output.
Address latch enable (ALE).
Asserted when an address is output
and negated when data is input or
output.
Read enable (RE).
Reads data at the falling edge of
RE.
Write enable.
Flash memory latches a command,
address, and data at the rising edge
of WE.
Ready/busy.
Indicates ready state at a high level
or busy state at a low level.
8-bit general I/O port.
8-bit general I/O port.
8-bit general I/O port.
8-bit general I/O port.
8-bit general I/O port.
8-bit general I/O port.
8-bit general I/O port.
8-bit general I/O port.
5-bit general I/O port.
8-bit general I/O port.
Rev. 1.00 Nov. 22, 2007 Page 26 of 1692
REJ09B0360-0100