SH7764 Datasheet, PDF (750/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
(5) Receive Operation
As with transmission the reception can be controlled in one of two ways: either DMA or an
interrupt driven.
Figures 18.21 and 18.22 show the flow of operation.
When disabling SSI_CH0 to SSI_CH5, the SSI clock must be supplied continuously until
SSI_CH0 to SSI_CH5 enter in the idle state, which is indicated by the IIRQ bits in SSISR0 to
SSISR5.
Note: * SCKD = 0: Clock input through the SSISCK[5:0] pins
SCKD = 1: Clock input through the AUDIO_CLK[5:0] pins
Rev. 1.00 Nov. 22, 2007 Page 694 of 1692
REJ09B0360-0100