SH7764 Datasheet, PDF (625/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
16.3.8 Master Address Register (ICMAR)
Bit: 7
Initial value: 0
R/W: R/W
6
0
R/W
5
4
3
SADD1[6:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
R/W
0
STM1
0
R/W
Bit
7 to 1
0
Bit Name Initial Value R/W
SADD1[6:0] All 0
R/W
STM1
0
R/W
Description
Slave Address
These bits are the address of the slave which
the master communicates with.
Slave Transfer Mode
This bit specifies the mode in which the slave
operates.
Bit STM1 sets the operating mode (transmit or
receive mode) of the slave, which is an
external slave device whose address matches
the slave address (SADD1) sent from the
master. The slave device is automatically set to
transmit/receive mode by hardware on
reception of the STM1 signal.
When this bit is set to 1, it indicates a read
operation, when this bit is cleared to 0, it
indicates a write operation.
16.3.9 Clock Control Register (ICCCR)
Bit: 7
Initial value: 0
R/W: R/W
6
0
R/W
5
4
SCGD[5:0]
0
0
R/W R/W
3
0
R/W
2
0
R/W
1
0
CDF[1:0]
0
0
R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 569 of 1692
REJ09B0360-0100