SH7764 Datasheet, PDF (1152/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
ROP Code
H'00
H'11
H'22
H'33
H'44
H'55
H'66
H'77
H'88
H'99
H'AA
H'BB
H'CC
H'DD
H'EE
H'FF
Operation
0
∼_{(S | D)}
∼_{S & D}
∼_S
S & ^∼D
∼_D
S^D
∼_{(S & D)}
S&D
∼_{(S ^ D)}
D
∼_{S | D}
S
S | ^∼D
S|D
1
Set the ROP code to H'CC when alpha blending is enabled (αE = 1). Neither alpha blending nor
raster operation is performed for the A value in the ARGB format. The A value is drawn
according to the source A value use (SAU) and A value (AVALUE) bits in the rendering control
register (RCLR).
Rev. 1.00 Nov. 22, 2007 Page 1096 of 1692
REJ09B0360-0100