SH7764 Datasheet, PDF (1014/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
generated regardless of whether the host controller function or function controller function has
been selected.
(10) DTCH Interrupt
The DTCH interrupt is generated if disconnection of the USB bus is detected when the host
controller function has been selected. This module detects bus disconnection based on USB
Specification 2.0.
After detecting the DTCH interrupt, this module controls hardware as described below
(irrespective of the set value of the corresponding interrupt enable bit). Software should terminate
all the pipes in which communications are currently carried out for the pertinent port and make a
transition to the wait state for bus connection to the pertinent port (wait state for ATTCH interrupt
generation).
(a) Modifies the UACT bit for the port in which a DTCH interrupt has been detected to 0.
(b) Puts the port in which a DTCH interrupt has been generated into the idle state.
(11) SACK Interrupt
The SACK interrupt is generated when an ACK response for the transmitted setup packet has been
received from the peripheral device with the host controller function selected. The SACK interrupt
can be used to confirm that the setup transaction has been completed successfully.
(12) SIGN Interrupt
The SIGN interrupt is generated when an ACK response for the transmitted setup packet has not
been correctly received from the peripheral device three consecutive times with the host controller
function selected. The SIGN interrupt can be used to detect no ACK response transmitted from the
peripheral device or corruption of an ACK packet.
(13) ATTCH Interrupt
The ATTCH interrupt is generated when J-state or K-state of the full-speed level signal is detected
on the USB port for 2.5 µs in host controller mode. To be more specific, the ATTCH interrupt is
detected on any of the following conditions.
(a) When K-state, SE0, or SE1 changes to J-state, and J-state continues 2.5 µs.
(b) When J-state, SE0, or SE1 changes to K-state, and K-state continues 2.5 µs.
Rev. 1.00 Nov. 22, 2007 Page 958 of 1692
REJ09B0360-0100