SH7764 Datasheet, PDF (1315/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit
Bit Name Value
21
VSYNC_ 0
TIM
20
HSYNC_ 0
TIM
19
DEV_TIM 0
18
DEH_TIM 0
17
DEC_TIM 0
16
COM_TIM 0
15 to 10 
All 0
Section 24 Video Display Controller (VDC2)
R/W Description
R/W Specifies the VSYNC/SPS output timing.
0: Outputs VSYNC/SPS at the rising edge of the
panel clock
1: Outputs VSYNC/SPS at the falling edge of the
panel clock
R/W Specifies the HSYNC/SPL output timing.
0: Outputs HSYNC/SPL at the rising edge of the
panel clock
1: Outputs HSYNC/SPL at the falling edge of the
panel clock
R/W Specifies the DEV/CLS output timing.
0: Outputs DEV/CLS at the rising edge of the panel
clock
1: Outputs DEV/CLS at the falling edge of the
panel clock
R/W Specifies the DEH/LP output timing.
0: Outputs DEH/LP at the rising edge of the panel
clock
1: Outputs DEH/LP at the falling edge of the panel
clock
R/W Specifies the DEC/PS output timing.
0: Outputs DEC/PS at the rising edge of the panel
clock
1: Outputs DEC/PS at the falling edge of the panel
clock
R/W Specifies the COM/CDE output timing.
0: Outputs COM/CDE at the rising edge of the
panel clock
1: Outputs COM/CDE at the falling edge of the
panel clock
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1259 of 1692
REJ09B0360-0100