SH7764 Datasheet, PDF (1562/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 User Debugging Interface (H-UDI)
31.5 Operation
31.5.1 TAP Control
Figure 31.3 shows the internal states of the TAP controller. The state transitions basically conform
to the JTAG standard.
• State transitions occur according to the TMS value at the rising edge of the TCK signal.
• The TDI value is sampled at the rising edge of the TCK signal and shifted at the falling edge of
the TCK signal.
• The TDO value is changed at the falling edge of the TCK signal. The TDO signal is in a Hi-Z
state other than in the Shift-DR or Shift-IR state.
• A transition to the Test-Logic-Reset by clearing TRST to 0 is performed asynchronously with
the TCK signal.
1 Test -Logic-Reset
0
1
0 Run-Test/Idle
1
Select-DR-Scan
0
1
Capture-DR
0
Shift-DR 0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR 0
1
0
Exit2-IR
1
Update-IR
1
0
Figure 31.3 TAP Controller State Transitions
Rev. 1.00 Nov. 22, 2007 Page 1506 of 1692
REJ09B0360-0100