SH7764 Datasheet, PDF (43/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 33.16 SRAM Bus Cycle in Bank Open Mode Pre-charge Write Bus Cycle
(PRE-ACT-SRITE) (BOMODE[1:0]= 00, SRP[1:0]= 00, SRCD=0,
IRP= 2cyc, IRCD= 2cyc)....................................................................................... 1595
Figure 33.17 SRAM Bus Cycle in Bank Open Mode Write Bus Cycle (WRITE)
(BOMODE[1:0]= 00, SRCD= 0, IRCD= 2cyc)..................................................... 1596
Figure 33.18 SRAM Bus Cycle in Bank Close Mode Read Bus Cycle (ACT-READA)
(BOMODE[1:0]= 1, SCL[2:0]= 000, SRCD= 0, IRP= 2cyc,
CAS Latency= 2cyc).............................................................................................. 1597
Figure 33.19 SRAM Bus Cycle in Bank Close Mode Write Bus Cycle (ACT-WRITEA)
(BOMODE[1:0]= 00, SWR[1:0]= 00, SRP[1:0]= 00, SRCD= 0,
IDAL= 4cyc, IRCD= 2cyc) ................................................................................... 1598
Figure 33.20 SRAM Bus Cycle in Pre-charge Cycle (PALL) (SRP[1:0]= 00, IRP= 2cyc) ........ 1599
Figure 33.21 SRAM Bus Cycle in Mode Register Setting Cycle (MRS).................................... 1600
Figure 33.22 SRAM Bus Cycle in Auto Refresh Cycle (REF)
(SRFC[2:0]= 000, IRC= 8cyc)............................................................................... 1601
Figure 33.23 SRAM Bus Cycle in Refresh Cycle (SREF) .......................................................... 1602
Figure 33.24 NMI Input Timing.................................................................................................. 1603
Figure 33.25 IRQ, PINT Input, IRQOUT Output Timing ........................................................... 1604
Figure 33.26 DREQ/DTEND/DACK Timing ............................................................................. 1605
Figure 33.27 TCLK Input Timing ............................................................................................... 1606
Figure 33.28 I²C Timing.............................................................................................................. 1607
Figure 33.29 AC Characteristics Load Condition ....................................................................... 1607
Figure 33.30 SCK Input Clock Timing ....................................................................................... 1608
Figure 33.31 SCIF Input/Output Timing in Clocked Synchronous Mode................................... 1608
Figure 33.32 Clock Input/Output Timing .................................................................................... 1609
Figure 33.33 SSI Transmit Timing (1) ........................................................................................ 1610
Figure 33.34 SSI Transmit Timing (2) ........................................................................................ 1610
Figure 33.35 SSI Receive Timing (1).......................................................................................... 1610
Figure 33.36 SSI Receive Timing (2).......................................................................................... 1611
Figure 33.37 AUDIO_CLK Timing ............................................................................................ 1611
Figure 33.38 PIO Data Transmission In-between Devices.......................................................... 1619
Figure 33.39 Multiword DMA Data Transmission Start ............................................................. 1620
Figure 33.40 Multiword Data Transmission................................................................................ 1621
Figure 33.41 End of Multiword Data Transmission from Device ............................................... 1622
Figure 33.42 End of Multiword Data Transmission from Host................................................... 1623
Figure 33.43 Ultra-DMA Data In-burst Start .............................................................................. 1624
Figure 33.44 Ultra-DMA Data In-burst....................................................................................... 1625
Figure 33.45 Ultra-DMA Data In-burst from Host Pause ........................................................... 1625
Figure 33.46 End of Ultra-DMA Data In-burst from Device ...................................................... 1626
Figure 33.47 End of Ultra-DMA Data In-burst from Host.......................................................... 1627
Rev. 1.00 Nov. 22, 2007 Page xliii of lvi