SH7764 Datasheet, PDF (838/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit
Bit Name
31 to 19 
Initial
Value
All 0
18 to 16 RFFO[2:0] 111
15 to 3 
All 0
2 to 0 RFDO[2:0] 111
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Receive Frame Count Overflow BSY Output Threshold
000: When two receive frames have been stored in the
receive FIFO.
001: When four receive frames have been stored in the
receive FIFO.
010: When six receive frames have been stored in the
receive FIFO.
:
110: When 14 receive frames have been stored in the
receive FIFO.
111: When 16 receive frames have been stored in the
receive FIFO.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Receive FIFO Overflow BSY Output Threshold
000: When (256 − 32) bytes of data is stored in the
receive FIFO.
001: When (512 − 32) bytes of data is stored in the
receive FIFO.
:
110: When (1792 − 32) bytes of data is stored in the
receive FIFO.
111: When (2048 − 32) bytes of data is stored in the
receive FIFO.
Rev. 1.00 Nov. 22, 2007 Page 782 of 1692
REJ09B0360-0100