SH7764 Datasheet, PDF (719/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit
10
9
8
7 to 5
4
3
2
Bit Name
DMENDM1
(DMENDM4)
Initial
Value
1
TXFIFOFULM1 1
(TXFIFOFULM4)
RXFIFOEMPM1 1
(RXFIFOEMPM4)

All 0
BLKENDM0
1
(BLKENDM3)
BLKNENDM0 1
(BLKNENDM3)
DMENDM0
1
(DMENDM3)
R/W Description
R/W DMEND1 (4) Interrupt Source Mask
Masks the DMEND1 (4) interrupt source.
0: The DMEND1 (4) interrupt source is not masked.
1: The DMEND1 (4) interrupt source is masked.
R/W TXFIFOFUL1 (4) Interrupt Source Mask
Masks the TXFIFOFUL1 (4) interrupt source.
0: The TXFIFOFUL1 (4) interrupt source is not masked.
1: The TXFIFOFUL1 (4) interrupt source is masked.
R/W RXFIFOEMP1 (4) Interrupt Source Mask
Masks the RXFIFOEMP1 (4) interrupt source.
0: The RXFIFOEMP1 (4) interrupt source is not
masked.
1: The RXFIFOEMP1 (4) interrupt source is masked.
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W BLKEND0 (3) Interrupt Source Mask
Masks the BLKEND0 (3) interrupt source.
0: The BLKEND0 (3) interrupt source is not masked.
1: The BLKEND0 (3) interrupt source is masked.
R/W BLKNEND0 (3) Interrupt Source Mask
Masks the BLKNEND0 (3) interrupt source.
0: The BLKNEND0 (3) interrupt source is not masked.
1: The BLKNEND0 (3) interrupt source is masked.
R/W DMEND0 (3) Interrupt Source Mask
Masks the DMEND0 (3) interrupt source.
0: The DMEND0 (3) interrupt source is not masked.
1: The DMEND0 (3) interrupt source is masked.
Rev. 1.00 Nov. 22, 2007 Page 663 of 1692
REJ09B0360-0100