SH7764 Datasheet, PDF (787/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.23 Random Number Generation Counter Upper Limit Setting Register (RDMLR)
RDMLR is used to set the upper limit for the counter used in the random number generation
block.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
RMD[19:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RMD[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 20 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
19 to 0 RMD[19:0]
All 0 R/W Upper Limit for Counter Used in Random Number
Generation Block
H'00000: Set value in normal operation
H'00001to H’FFFFE: Upper limit for the counter
Note: The operation of the random number generation block in the feLic depends on the setting in
this register. Accordingly, special attention should be paid when setting a value other than
0.
Rev. 1.00 Nov. 22, 2007 Page 731 of 1692
REJ09B0360-0100