SH7764 Datasheet, PDF (690/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit
7, 6
5, 4
3 to 0
Bit Name
Initial
Value R/W
RDMBSZ[1:0] 00
R/W
WDMBSZ[1:0] 00
R/W

All 0 R
Description
RDMA Maximum Burst Size
These bits set the maximum burst size during RDMA
data transfer.
00: 1 burst (8 bytes)
01: 2 bursts (16 bytes)
10: 4 bursts (32 bytes)
11: Setting prohibited
WDMA Maximum Burst Size
These bits set the maximum burst size during
WDMA data transfer.
00: 1 burst (8 bytes)
01: 2 bursts (16 bytes)
10: 4 bursts (32 bytes)
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
18.3.2 RDMA Transfer Source Address Registers 0 to 5 (SSIRDMADR0 to
SSIRDMADR5)
SSIRDMADR0 to SSIRDMADR5 is a 32-bit readable/writable register that set the data transfer
source address during RDMA transfer other than the port function. This register value is initialized
when either of the conditions is implemented such as hardware reset, software reset or software
reset for SSI_DMAC (DMRST bit in SSIDMACOR0 to SSIDMACOR3). To be written to this
register, DMEN bit in SSIDMCOR0 to SSDMCOR5 must be 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDMADR[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RDMADR[15:3]



Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
Rev. 1.00 Nov. 22, 2007 Page 634 of 1692
REJ09B0360-0100