SH7764 Datasheet, PDF (1323/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.22 Gate Control Signal Timing Control Register (COMTIM)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COM_
MODE





COMTIM_V[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





COMTIM_H[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31
COM_MODE 0
R/W Selects the gate control signal (COM) toggle mode.
0: Toggles the signal output in every line in an
alternating sequence of high and low and
inverts the phase in every frame (when the
sequence in frame n is high -> low -> high ..., it
is inverted to low -> high -> low ... in frame n +
1).
1: Toggles the signal output in every frame.
30 to 26 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 COMTIM_V H'000 R/W These bits specify in number of lines the interval
[9:0]
between the internal vertical sync signal and the
frame start position of the gate control signal
(COM). A value of 0 specifies that a frame starts in
the first line, and a value of 1 specifies that a frame
starts in the second line.
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0 COMTIM_H H'000 R/W These bits specify in number of panel clock cycles
[10:0]
the horizontal interval between the internal
horizontal sync signal and the position where the
gate control signal (COM) toggles.
Note: Be sure to satisfy COMTIM_V < SYN_HEIGHT; otherwise, correct operation is not
guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1267 of 1692
REJ09B0360-0100