SH7764 Datasheet, PDF (519/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
Program execution state
Yes
ICR0.MAI = 1?
No
Yes
NMI input is low?
No
No
Interrupt
generated?
Yes
SR.BL = 0 or
Yes
Sleep mode?
No
No
ICR0.NMIB = 1?
Yes
NMI?
No
No
NMI?
Yes
Yes
Level 15
No
interrupt?
Yes
Level 14
No
interrupt?
Yes
SR.IMASK level
Yes
is 14 or low
Level 1
No
interrupt?
No ^Yes
SR.IMASK level
Yes
is 13 or low
No
CPUOPM.INTMU = 1?
No
Yes
SR.IMASK level
is 0?
No
Yes
Set SR.IMASK to
accepted interrupt level
Set interrupt source
code in INTEVT
Save SR to SSR;
save PC to SPC;
save R15 to SGR
Branch to
exception handling routine
Figure 13.3 Interrupt Operation Flowchart
Rev. 1.00 Nov. 22, 2007 Page 463 of 1692
REJ09B0360-0100