SH7764 Datasheet, PDF (1003/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
(ii) For the pipe in the receiving direction
 For the pipe for isochronous transfers, when the time to issue an IN token comes in a state
in which there is no space available in the FIFO buffer.
In this case, this module discards the received data for the IN token, setting the PIPENRDY
bit of the corresponding pipe and the OVRN bit to 1.
When a packet error is detected in the received data for the IN token, this module also sets
the CRCE bit to 1.
 For the pipe for the transfers other than isochronous transfers, when any combination of the
following two cases occur three consecutive times: 1) no response is returned from the
peripheral device for the IN token issued by this module (when timeout is detected before
detection of the DATA packet from the peripheral device) and 2) an error is detected in the
packet from the peripheral device.
In this case, this module sets the corresponding PIPENRDY bit to 1 and modifies the
setting of the PID bits of the corresponding pipe to NAK.
 For the pipe for isochronous transfers, when no response is returned from the peripheral
device for the IN token (when timeout is detected before detection of the DATA packet
from the peripheral device) or an error is detected in the packet from the peripheral device.
In this case, this module sets the corresponding PIPENRDY bit to 1. (The setting of the
PID bits of the corresponding pipe to NAK is not modified.)
 For the pipe for isochronous transfers, when a CRC error or a bit stuffing error is detected
in the received data packet.
In this case, this module sets the corresponding PIPENRDY bit and CRCE bit to 1.
 When the STALL handshake is received.
In this case, this module sets the corresponding PIPENRDY bit to 1 and modifies the
setting of the PID bits of the corresponding pipe to STALL.
Rev. 1.00 Nov. 22, 2007 Page 947 of 1692
REJ09B0360-0100