SH7764 Datasheet, PDF (652/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.3 Interrupt Enable (ATAPI_INT_ENABLE)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
— iSWERR iIFERR iDNEND iDEVTRM iDEVINT iTOUT iERR iNEND iACT
Initial value: ⁰
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ^R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 9 —
All 0
R
Reserved
8
iSWERR 0
R/W iSWERR is SWERR interrupt enable.
7
iIFERR
0
R/W iIFERR is IFERR interrupt enable.
6
iDNEND
0
R/W iDNEND is DNEND interrupt enable.
5
iDEVTRM 0
R/W iDEVTRM is DEVTRM interrupt enable
4
iDEVINT 0
R/W iDEVINT is DEVINT interrupt enable.
3
iTOUT
0
R/W iTOUT is TOUT interrupt enable.
2
iERR
0
R/W iERR is ERR interrupt enable.
1
iNEND
0
R/W iNEND is NEND interrupt enable.
0
iACT
0
R/W iACT is ACT interrupt enable. Since ACT is cleared
automatically when a DMA transfer is completed,
this bit should not be set to 1.
Note: Writing 1 to each bit enables the interrupt signal of the ATAPI status register bit.
Rev. 1.00 Nov. 22, 2007 Page 596 of 1692
REJ09B0360-0100