SH7764 Datasheet, PDF (1384/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
The number of output data units obtained as conversion result can be calculated by using the
following expression (A) or (B). Table 26.5 shows the relationship of setting value and applicable
formula between IFS and OFS[1:0].
Number
of
output
data
=
Number
of
input
data
×
Output sampling rate
Input sampling rate
Number
of
output
data
=
Number
of
input
data
×
Output sampling rate
Input sampling rate
-1
... (A)
... (B)
Table 26.5 Relationship between Sampling Rate Setting and Number of Output Data
OFS[1:0]
Value
(Output
Sampling
Rate
0000
(kHz)) (8.0)
00 (44.1) B
01 (48.0) B
10 (32.0) A
IFS [3:0]Setting (Input Sampling Rate [kHz])
0001
0010
(11.025) (12.0)
A
A
B
A
B
B
0100
(16.0)
B
B
A
0101
(22.05)
A
B
B
0110
(24.0)
A
A
A
1000
(32.0)
B
B

1001
(44.1)

B
B
1010
(48.0)
A

A
26.2.6 SRC Status Register (SRCSTAT)
SRCSTAT is a 16-bit readable/writable register that indicates the number of data units in the input
and output data FIFOs, whether the various interrupt sources have been generated or not, and the
flush processing status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OFDN[3:0]
IFDN[4:0]
-
-
FLF
- OVF IINT OINT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written after having read as 1.
Bit
Bit Name
15 to 12 OFDN[3:0]
Initial
Value
All 0
R/W
R
Description
Output FIFO Data Count
Indicates the number of data units in the output FIFO.
Rev. 1.00 Nov. 22, 2007 Page 1328 of 1692
REJ09B0360-0100