SH7764 Datasheet, PDF (1673/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Electrical Characteristics
Table 33.25 Symbol for ATAPI Interface Ultra-DMA Transmission Timing
Symbol
t2CYCTYP
tCYC
t2CYC
tDS
tDH
tDVS
tDVH
tCS
tCH
tCVS
tCVH
tZFS
tDZFS
tFS
tLI
tMLI
tUI
tAZ
tZAH
tZAD
tENV
tRFS
tRP
tIORDYZ
tZIORDY
tACK
tSS
Note
Average cycle time (2 cycles)
Cycle time
Minimum cycle time (2 cycles)
Data setup time (receive side)
Data hold time (receive side)
Data setup time (transfer side)
Data hold time (transfer side)
CRC data setup time (receive side)
CRC data hold time (receive side)
CRC setup time (transfer side)
CRC hold time (transfer side)
Setup time from the strove state to the drive state of the active signal
(transfer side)
Setup time from the drive state to the first strove state of the active signal
(transfer side)
Initial STROBE time
Interlock time with restriction
Minimum interlock time
Interlock time without restriction
Output release time
Output delay time
Output defined time (from release)
Envelope time
Final STROBE time
Time till assert the STOP or negate the DMARQ
Time till release the IORDY
Time till drive the STROBE
Time for DMACK setup/hold
Time for STROBE STOP
Rev. 1.00 Nov. 22, 2007 Page 1617 of 1692
REJ09B0360-0100