SH7764 Datasheet, PDF (695/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
31
DMRST 0
W
SSI_DMAC0/1 Software Reset
Resets the SSI_DMAC0/1 of corresponding channel
among SSI_CH0 to SSI_CH5, and stops data transfer.
This bit is always read as 0.
0: The software reset is disabled.
1: The software reset is enabled.
30
TXRST 0
R/W Transmit FIFO Buffer Reset
Resets the transmit FIFO buffer.
0: The transmit FIFO buffer reset is disabled.
1: The transmit FIFO buffer reset is enabled.
29
RXRST 0
R/W Receive FIFO Buffer Reset
Resets the receive FIFO buffer.
0: The receive FIFO buffer reset is disabled.
1: The receive FIFO buffer reset is enabled.
28 to 13 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 639 of 1692
REJ09B0360-0100