SH7764 Datasheet, PDF (804/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.6 Usage Notes
Attention should be paid to the following when the EtherC is used.
(1) Conditions for setting the LCHNG bit
The LCHNG bit in the ECSR register may be set even when the input level on the LNKSTA pin
has not changed. It may be set when the LNKSTA pin is selected by the PSEL bit in the GPIO or
when a high level is applied to the LNKSTA pin while the EtherC/E-DMAC is released from the
software reset state by the SWR bit in the EDMR register.
This is because the LNKSTA signal is internally fixed low regardless of the external pin level
when the LNKSTA pin is not selected by the GPIO or while the EtherC/E-DMAC is in the
software reset state,.
In order not to request the LINK signal change interrupt accidentally, clear the LCHNG bit before
setting the LCHNGIP bit in the ECSIPR register.
Rev. 1.00 Nov. 22, 2007 Page 748 of 1692
REJ09B0360-0100