SH7764 Datasheet, PDF (18/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface (IIC)..................................................................... 555
16.1 Features.............................................................................................................................. 555
16.2 Input/Output Pins............................................................................................................... 556
16.3 Register Descriptions......................................................................................................... 556
16.3.1 Slave Control Register (ICSCR)........................................................................... 558
16.3.2 Slave Status Register (ICSSR).............................................................................. 559
16.3.3 Slave Interrupt Enable Register (ICSIER) ............................................................ 562
16.3.4 Slave Address Register (ICSAR).......................................................................... 563
16.3.5 Master Control Register (ICMCR) ....................................................................... 564
16.3.6 Master Status Register (ICMSR) .......................................................................... 566
16.3.7 Master Interrupt Enable Register (ICMIER) ........................................................ 568
16.3.8 Master Address Register (ICMAR) ...................................................................... 569
16.3.9 Clock Control Register (ICCCR).......................................................................... 569
16.3.10 Receive and Transmit Data Registers (ICRXD and ICTXD) ............................... 571
16.4 Operations.......................................................................................................................... 572
16.4.1 Data and Clock Filters .......................................................................................... 572
16.4.2 Clock Generator.................................................................................................... 572
16.4.3 Master/Slave Interfaces......................................................................................... 572
16.4.4 Software Status Interlocking................................................................................. 572
16.4.5 I²C Bus Data Format ............................................................................................. 574
16.4.6 7-Bit Address Format............................................................................................ 575
16.4.7 10-Bit Address Format.......................................................................................... 576
16.4.8 Master Transmit Operation................................................................................... 578
16.4.9 Master Receive Operation .................................................................................... 580
16.5 Programming Examples..................................................................................................... 582
16.5.1 Master Transmitter................................................................................................ 582
16.5.2 Master Receiver .................................................................................................... 583
16.5.3 Master Transmitter - Restart - Master Receiver.................................................... 584
Section 17 ATAPI ............................................................................................. 587
17.1 Features.............................................................................................................................. 587
17.2 Input/Output Pins............................................................................................................... 588
17.3 Register Description .......................................................................................................... 589
17.3.1 ATAPI Control (ATAPI_CONTROL) ................................................................. 592
17.3.2 ATAPI Status (ATAPI_STATUS) ....................................................................... 594
17.3.3 Interrupt Enable (ATAPI_INT_ENABLE)........................................................... 596
17.3.4 PIO Timing Register (ATAPI_PIO_TIMING)..................................................... 597
17.3.5 Multiword DMA Timing Register (ATAPI_MULTI_TIMING).......................... 598
17.3.6 Ultra DMA Timing Register (ATAPI_ULTRA_TIMING) .................................. 600
17.3.7 Descriptor Table Base Address Register (ATAPI_DTB_ADR)........................... 601
Rev. 1.00 Nov. 22, 2007 Page xviii of lvi