SH7764 Datasheet, PDF (1033/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Table 21.24 FIFO Port Function Settings
Register Name
C/DnFIFOSEL
C/DnFIFOCTR
Bit Name
RCNT
REW
DCLRM
DREQE
MBW
BIGEND
ISEL
CURPIPE
BVAL
BCLR
DTLN
Function
Note
Selects DTLN read mode
Buffer memory rewind (re-read,
rewrite)
Automatically clears data received for For DnFIFO only
a specified pipe after the data has
been read
Enables DMA transfers
For DnFIFO only
FIFO port access bit width
Selects FIFO port endian
FIFO port access direction
Selects the current pipe
For DCP only
Ends writing to the buffer memory
Clears the buffer memory on the CPU
side
Checks the length of received data
(a) FIFO Port Selection
Table 21.25 shows the pipes that can be selected with the various FIFO ports. The pipe to be
accessed is selected using the CURPIPE bit in C/DnFIFOSEL. After the pipe is selected, whether
the CURPIPE value for the pipe which was written last can be correctly read should be checked.
(If the previous pipe number is read, it indicates that the pipe modification is being executed by
this module.) Then, the FIFO port can be accessed after FRDY = 1 is checked .
Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory
access direction conforms to the DIR bit in PIPEnCFG. The ISEL bit determines this only for the
DCP.
Table 21.25 FIFO Port Access Categorized by Pipe
Pipe
DCP
PIPE1 to PIPE9
Access Method
CPU access
CPU access
DMA access
Port that can be Used
CFIFO port register
CFIFO port register
D0FIFO/D1FIFO port register
D0FIFO/D1FIFO port register
Rev. 1.00 Nov. 22, 2007 Page 977 of 1692
REJ09B0360-0100